In a typical analog CMOS fabrication process, capacitors are usually realized using polysilicon-to-polysilicon layers. In this realization, two layers of polysilicon sandwich a thin silicon dioxide (SiO2) layer. This structure usually creates a relatively high capacitance per area so that the real estate chip area remains low and thus the cost of realizing the capacitor remains low. The capacitor density realized by these two layers is in the order of a few femto-farads per square micron (fF/μm2).
However, in a typical digital CMOS fabrication process, because two layers of polysilicon may not be available, capacitors may be realized using metal-to-metal layers. The capacitor density realized by two metal layers is usually even lower because the oxide between these two layers is even thicker than the polysilicon-to-polysilicon layer available in an analog CMOS process. Therefore, realizing a physically large capacitor on the integrated circuit (IC) is very costly in any integrated circuit process unless special fabrication process steps have been added to implement it. However, fabrication process modification may be very costly. IC designers usually consider capacitors higher than 100 pF a physically large capacitor with unreasonable fabrication costs and therefore such a large capacitor can be avoided unless there is no choice or the benefit of having such a large capacitor outweighs its real-estate cost.
When considering the use of large capacitors for noise attenuation in a typical CMOS image sensor, the voltages on a floating diffusion of the image sensor pixels are sensed by a gate of a transistor which is configured as a source-follower amplifier. DC bias currents in source-amplifiers of a single row are supplied by a series of current sources. One of the sources of noise in CMOS image sensors is row-wise temporal noise. This noise shows up as strips that change their locations every time a new frame of an image is captured. The strips are not spatially fixed or stationary and their locations are a function of time, thus the term temporal noise.
FIG. 1 depicts a simplified circuit diagram 100 comprising a row of image sensor pixels and their associated bias current sources 107 connected between ground 101 and VAAPIX supply 102. Each image sensor pixel comprises floating diffusion photodiode 103 and source follower amplifier 104 of which are selected by row select transistor 105. As shown in FIG. 1, the VLN line (node 106) is a single DC voltage set by diode connected transistor M1 109, that supplies bias voltage to all bias current sources 107. In this layout, the VLN line 106 is usually a metal layer that extends across the image sensor pixel array from one side of the imaging integrated circuit (IC) to the other. Depending on the size of the CMOS image sensor, VLN line 106 can be a few millimeters long, which is much larger than a typical layout trace. This long trace, being a relatively high impedance line, acts as an antenna in the IC that can pick up noise from any noisy environment (digit switching, ground bounces, supply bounces, etc.).
In the CMOS image sensor, such as the image sensor 100 depicted in FIG. 1, one of the mechanisms that causes a source of noise, referred to as row-wise temporal noise, is the temporal noise developed on the VLN line 106. By placing a capacitor 108 between VLN line node 106 to ground 101, it is possible to filter out (attenuate) some of the noise present on the VLN line. However, this capacitor is required to be large due to the row-wise temporal noise frequency being in the low frequency range. The capacitor 108 between VLN line 106 and ground 101 and the small signal resistance created by the trans-conductance (1/gm) of the diode connected transistor M1 109, form a low pass filter that attenuates the noise on the VLN line. The larger the capacitor, the lower the pole of the low-pass filter, thus producing a quieter DC bias voltage on the VLN line. To improve the row-wise temporal noise, the capacitor should be in the range of several hundreds of pico-farad up to a few nano-farad, which presents a major fabrication obstacle in creating the large noise attenuating capacitor needed. Due to limited space on the IC die, the physical size of capacitor needed to attenuate the row-wise temporal noise is prohibitive.
Therefore, what is needed in the art for integrated circuits is a way to effectively attenuate temporal noise by providing an effective large capacitance, which, in conjunction with other circuit elements will create a low pass frequency filter that may be used to reduce row-wise temporal noise, such as in a CMOS image sensor device.